1. Field of the Invention
The present invention relates to a semiconductor integrated circuit capable of testing a memory by carrying out a built-in self-test, and more particularly to a semiconductor integrated circuit capable of testing a memory operating at high speed. The present invention also relates to a memory test method.
2. Prior Art
In recent years, as the LSI technology progresses, the operation speeds of memories included in semiconductor integrated circuits have become increasing. In order to test these memories, a built-in self-test (the so-called BIST) is generally used.
FIG. 21 shows a circuit block for carrying out a BIST. In FIG. 21, numeral 401 designates a BIST circuit, and numeral 402 designates a memory to be subjected to a BIST. A first clock (memory clock) is input to the memory 402, and a second clock (BIST clock) is input to the BIST circuit 401. The memory 402 is classified into an ordinary data rate memory operating in synchronization with the rising edge or the falling edge of a clock and a double data rate memory operating in synchronization with both the rising and falling edges of the clock.
From the BIST circuit 401 to the memory 402, addresses and data are input, and control signals, such as a write enable signal, are also input. In addition, the output (Data-Out) of the memory 402 is input to the BIST circuit 401 and an ordinary logic circuit. Furthermore, an expected value comparison circuit inside the BIST circuit 401 compares the data input from the memory 402 with an expected value, thereby carrying out a pass/fail judgment.
FIG. 22 shows clock timing at the time when a BIST is carried out for the memory 402 in the case when the memory 402 is a double data rate (DDR: Double Data Rate) memory. In addition, FIG. 22 shows the first clock (Memory Clock), the second clock (BIST Clock) and the data output (Data-Out) of the memory 402.
The memory 402, a DDR memory, can operate in synchronization with both the rising and falling edges of the first clock (Memory Clock). Hence, in the case when a read operation is carried out, for example, data is output at the rising edge of the first clock (Memory Clock) at time t1 of FIG. 22, and the next data is output at the falling edge of the first clock (Memory Clock) at time t2.
In the BIST circuit 401 for testing this kind of memory 402, by setting the rising edges of the second clock (BIST Clock) at times t1, t2, . . . , tn, the DDR memory can be tested at its actual operation speed.
In the BIST circuit 401 for testing the high-speed memory 402, it is necessary to increase the operation speed of the BIST circuit 401 itself depending on the operation speed of the memory 402.
In the case when a memory operates at the double speed of the clock frequency, just like the above-mentioned DDR memory, or in the case when a memory that operates at very high speed is tested at its actual operation speed, the BIST circuit itself is required to be operated at the high speed. However, since the operation frequency of the memory is very high, it is difficult to attain a BIST circuit capable of operating at such a high operation frequency, thereby causing a problem of attaining such a BIST circuit.
In addition, cells having high drive capability are required for high-speed operation, thereby causing a problem of increasing the area of the BIST circuit. Furthermore, the clock frequency of the BIST circuit is required to be raised for high-speed operation, thereby causing a problem of increasing the power consumption of the BIST circuit.